The present invention relates to multiple layer circuits of an electronic device and its manufacturing method, particularly relates to an electronic device effective when the electronic device is applied to a Josephson integrated circuit device.
Various devices are made in the arrangement and the wiring of elements included in a highly integrated electronic device. Particularly, for high-density integration, reliable multilevel wiring is important. A process for planarizing an insulation layer provided after a wiring pattern of each layer is formed is applied to a high-density integrated electronic device so as to form multilevel wiring. For this process, chemical mechanical polishing (CMP), spin-on film etchback, bias sputtering, lift-off and others have been used independently or in the combination of these (for example, a non-patent document 1, a non-patent document 2 and a non-patent document 3).
Besides, though the following method is more complex, a method of newly adding processes for photolithography and etching and planarizing in two-stage processes has been proposed (for example, patent documents 1 and 2).    [Non-patent document 1] S. Nagasawa et al, Planarization Technology for Josephson Integrated Circuit, IEEE EDL. Vol. 9, p. 414 (1988).    [Non-patent document 2] M. B. Ketchen et al, Sub-μm, planarized, Nb—AlOx—Nb Josephson process for 125 mm wafers developed in partnership with Si technology, APL(Applied Physics Letters) vol. 59, p. 2609 (1991).    [Non-patent document 3] K. Kikuchi et al, New Fabrication Process of Josephson Tunnel Junctions Using Photosensitive Polyimide Insulation Layer for Superconducting Integrated Circuits, ASC(Applied Superconductivity Conference) 2002, 1EH05    [Patent document 1] JP-A-7-147278    [Patent document 2] JP-A-2003-324221